Computer Architecture Reading List
This list is likely to expand.
- A. Bhattacharjee, D. Lustig and M. Martonosi, Shared Last-Level TLBs for Chip Multiprocessors, Proceedings of the 17th International Symposium on
High-Performance Computer Architecture, pp.62-73
- H. W. Tseng and D. M. Tullsen, Data-Triggered Threads: Eliminating Redundant Computation, Proceedings of the 17th International Symposium on
High-Performance Computer Architecture, pp. 181-192
- F. Chen, R. Lee and X. Zhang, Essential Roles of Exploiting Internal Parallelism of Flash Memory base Solid State Drives in High-Speed Data Processing, Proceedings of the 17th International Symposium on
High-Performance Computer Architecture, pp. 266-277
- Y. Zhang and J. D. Owens, A Quantitative Performance Analysis Model for GPU Architectures, Proceedings of the 17th International Symposium on
High-Performance Computer Architecture, pp. 382-393
- O. Anderson, E. Fortuna, L. Ceze and S. Eggers, Checked Load: Architectural Support for JavaScript Type-Checking on Mobile Processors, Proceedings of the 17th International Symposium on
High-Performance Computer Architecture, pp. 419-430
- A. Seznec, Storage Free Confidence Estimation for the TAGE branch predictor, Proceedings of the 17th International Symposium on
High-Performance Computer Architecture, pp. 443-454